1. Field of the Invention
The present invention relates to a delay circuit and, particularly, to a delay circuit having delay characteristics that are dependent on temperature.
2. Description of Related Art
A semiconductor device generally has temperature characteristics such that characteristics vary with temperature. Signal delay characteristics are one of such temperature characteristics. The signal delay characteristics exhibit a positive temperature coefficient showing an increase in delay with an increase in temperature if an operating power supply voltage is high. If, on the other hand, an operating power supply voltage is low, the delay characteristics exhibit a negative temperature coefficient showing an increase in delay with a decrease in temperature. A semiconductor device includes a delay circuit for adjusting the signal timings. In a delay circuit, the delay characteristics also exhibit a negative temperature coefficient if an operating power supply voltage is low.
Recent semiconductor devices operate at a low operating power supply voltage. Particularly, there is an increasing demand for the reduction of power consumption through the use of a lower voltage for a memory of a portable device, a logic device, or the like. Accordingly, the negative temperature coefficient of the signal delay characteristics becomes more pronounced in such semiconductor devices. A large negative temperature coefficient of the signal delay characteristics causes difficulty in timing adjustment with an external input signal, which requires a decrease in operating speed. A technique for reducing a negative temperature coefficient of the delay characteristics of a delay circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2003-273712 (which is referred to hereinafter as a related art).
A delay circuit is typically configured as a multi-stage delay circuit which includes a plurality of delay circuits connected in multiple stages. FIG. 15 shows a circuit diagram of a multi-stage delay circuit 100 according to the related art. As shown in FIG. 15, the multi-stage delay circuit 100 includes delay circuits 101 and 102 which are connected in series. In each of the delay circuits 101 and 102, a resistor R and a capacitor which is composed of a MOS transistor MC are connected to the output of an inverter INV.
The capacitor which is used in the multi-stage delay circuit 100 is formed using a parasitic capacitor of a MOS transistor MC. A capacitance value of the capacitor is small when the MOS transistor MC is nonconductive and it is large when the MOS transistor MC is conductive. A threshold voltage of the MOS transistor MC has the temperature characteristics.
For example, a threshold voltage of a MOS transistor MC which is composed of a PMOS transistor becomes higher as a temperature increases. On the other hand, a threshold voltage of a MOS transistor MC which is composed of an NMOS transistor becomes lower as a temperature increases. Thus, a voltage range where a capacitance value of a capacitor is large becomes wider as a temperature increases. Accordingly, a time constant that is determined by the resistor R and the capacitor becomes higher as a temperature increases. Further, a delay time of an output signal of the delay circuits 101 and 102 becomes longer as a temperature increases. Thus, the multi-stage delay circuit 100 reduces a negative temperature coefficient of the delay characteristics of the delay circuit as a whole with the use of the temperature characteristics of the parasitic capacitor of the MOS transistor MC.
The multi-stage delay circuit 100 also includes reset transistors RTr. The reset transistor RTr of the delay circuit 101 causes an output signal of the delay circuit 101 to rise rapidly. On the other hand, the reset transistor RTr of the delay circuit 102 causes an output signal of the delay circuit 102 to fall rapidly. Thus, the reset transistor RTr causes either the rise or fall of the output signals of the delay circuits 101 and 102 to occur rapidly.
In the multi-stage delay circuit 100, a delayed signal is input to an inverter INV of a delay circuit which is connected in the subsequent stage. Further, the delay circuits are the inversion of each other. For example, if a delay circuit in one stage delays a rising edge, the delay circuit outputs a falling edge with a delay at the rising edge of an input signal. Then, a delay circuit in the subsequent circuit outputs a rising edge with a delay at the falling edge of the signal from the delay circuit in the previous stage.
However, the present inventors have recognized the followings. In the multi-stage delay circuit 100, the reset transistor RTr becomes nonconductive in response to the input signal IN. Thus, the timing when the output of each delay circuit starts changing corresponds to a timing when the output of the inverter INV changes. The output of the inverter INV of the delay circuit 101 in the first stage changes when the PMOS transistor P1 becomes nonconductive after the NMOS transistor N1 becomes conductive. The NMOS transistor N1 is a high-threshold transistor, and the PMOS transistor P1 is a low-threshold transistor. A delay occurs until the PMOS transistor P1 becomes nonconductive after the NMOS transistor N1 becomes conductive. The delay causes a delay in the inverter. On the other hand, the output of the inverter INV of the delay circuit 102 in the subsequent stage changes when the NMOS transistor N2 becomes nonconductive after the PMOS transistor P2 becomes conductive. The PMOS transistor P2 is a high-threshold transistor, and the NMOS transistor N2 is a low-threshold transistor. A delay occurs until the NMOS transistor N2 becomes nonconductive after the PMOS transistor P2 becomes conductive. The delay causes a delay in the inverter.
FIG. 16 shows a timing chart of the operation of the multi-stage delay circuit 100 according to the related art. As shown in FIG. 16, the multi-stage delay circuit 100 generates a delay time A after the input of the inverter INV of each delay circuit changes, which changes its output. Because the delay time A is a delay of the inverter INV, it has the temperature characteristics in accordance with the temperature characteristics of the transistor threshold. The temperature characteristics of the delay time A exhibits a negative temperature coefficient as in other circuits. If the negative temperature coefficient of the delay time A is larger than a positive temperature coefficient of a delay time that is generated by a resistor and a capacitor, it is unable for the multi-stage delay circuit 100 to generate a delay time of the entire circuit which exhibits a positive temperature coefficient. In other words, in the delay circuit of the related art, a positive temperature coefficient of the delay time which is generated by a resistor and a capacitor is cancelled by a negative temperature coefficient of the delay time of the inverter INV. Further, because the temperature characteristics of the delay time which is generated by the multi-stage delay circuit 100 are a mixture of a negative temperature coefficient of the delay time of the inverter INV and a positive temperature coefficient of the delay time generated by a resistor and a capacitor, the calculation of a delay time is complicated and it is difficult to set a delay time accurately.